MARC details
| 000 -LEADER |
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| fixed length control field |
02099nam a2200241 a 4500 |
| 001 - CONTROL NUMBER |
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| control field |
vtls000037710 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
KUKTEM |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20251114204418.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
090612t2008 my a f m 000 0 eng|d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
THE0006894(Local) |
| 039 #9 - LEVEL OF BIBLIOGRAPHIC CONTROL AND CODING DETAIL [OBSOLETE] |
|---|
| Level of rules in bibliographic description |
201906131010 |
| Level of effort used to assign nonsubject heading access points |
aida |
| Level of effort used to assign subject headings |
201107132243 |
| Level of effort used to assign classification |
VLOAD |
| Level of effort used to assign subject headings |
200908141628 |
| Level of effort used to assign classification |
VLOAD |
| Level of effort used to assign subject headings |
200908141602 |
| Level of effort used to assign classification |
VLOAD |
| -- |
200906121529 |
| -- |
ida84 |
| 040 ## - CATALOGING SOURCE |
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| Original cataloging agency |
UMP |
| 090 ## - LOCALLY ASSIGNED LC-TYPE CALL NUMBER (OCLC); LOCAL CALL NUMBER (RLIN) |
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| Classification number (OCLC) (R) ; Classification number, CALL (RLIN) (NR) |
TK7868.D5 R67 2008 rs Bc. |
| 100 0# - MAIN ENTRY--PERSONAL NAME |
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| Personal name |
Rosmira Roslan |
| 245 10 - TITLE STATEMENT |
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| Title |
Chess digital clock / |
| Statement of responsibility, etc. |
Rosmira Binti Roslan |
| 246 3# - VARYING FORM OF TITLE |
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| Title proper/short title |
Chess digital clock |
| Medium |
[electronic resource] |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
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| Place of publication, distribution, etc. |
Kuantan, Pahang : |
| Name of publisher, distributor, etc. |
UMP, |
| Date of publication, distribution, etc. |
2008 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
44 p. : |
| Other physical details |
ill. ; |
| Dimensions |
30 cm. |
| 502 ## - DISSERTATION NOTE |
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| Dissertation note |
Project paper (Bachelor in Electrical Engineering (Electronics)) -- Universiti Malaysia Pahang - 2008 |
| 520 3# - SUMMARY, ETC. |
|---|
| Summary, etc. |
The purpose of my project is to design and implement of the Chess Digital Clock. The project employs ISE software (ISE Design Suite 10.1) and implementation on Field-Programmable Gate Arrays (FPGAs) Xilinx board. It is a new technique for testing the interconnects of an arbitrary design mapped into an FPGA. Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. The experimental result on various benchmarks using the ISE software is on its simulation. The software is designed using VHDL code. Digital circuit modeling with hardware description languages (HDLs) is the key to modern design of integrated circuits (ICs). The state-of-the-art technique of designing complex digital systems and integrated circuits is to apply an HDL-based CAD approach, in which a high-level, text-based, abstract description of the circuit is created, then synthesized to a hardware implementation in a selected technology, and finally verified for its functionality and timing. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Digital electronics |