MARC details
| 000 -LEADER |
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| fixed length control field |
02315nam a2200253 a 4500 |
| 001 - CONTROL NUMBER |
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| control field |
vtls000056065 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
KUKTEM |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20251117150456.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
111118t2011 si a f 001 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9780470828496 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
0470828498 |
| 039 #9 - LEVEL OF BIBLIOGRAPHIC CONTROL AND CODING DETAIL [OBSOLETE] |
|---|
| Level of rules in bibliographic description |
201202021024 |
| Level of effort used to assign nonsubject heading access points |
asmadi |
| -- |
201111181042 |
| -- |
sri |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
UMP |
| 090 ## - LOCALLY ASSIGNED LC-TYPE CALL NUMBER (OCLC); LOCAL CALL NUMBER (RLIN) |
|---|
| Classification number (OCLC) (R) ; Classification number, CALL (RLIN) (NR) |
TK7895.E42 B35 2011 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Bailey, Donald G. |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Design for embedded image processing on FPGAs / |
| Statement of responsibility, etc. |
Donald G. Bailey |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
Singapore : |
| Name of publisher, distributor, etc. |
Wiley, |
| Date of publication, distribution, etc. |
2011 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xvi, 482 p. : |
| Other physical details |
ill. (some col.) ; |
| Dimensions |
26 cm. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc. note |
Includes bibliographical references and index |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
"Introductory material will consider the problem of embedded image processing, and how some of the issues may be solved using parallel hardware solutions. Field programmable gate arrays (FPGAs) are introduced as a technology that provides flexible, fine-grained hardware that can readily exploit parallelism within many image processing algorithms. A brief review of FPGA programming languages provides the link between a software mindset normally associated with image processing algorithms, and the hardware mindset required for efficient utilization of a parallel hardware design. The bulk of the book will focus on the design process, and in particular how designing an FPGA implementation differs from a conventional software implementation. Particular attention is given to the techniques for mapping an algorithm onto an FPGA implementation, considering timing, memory bandwidth and resource constraints, and efficient hardware computational techniques. Extensive coverage will be given of a range of image processing operations, discussing efficient implementations and how these may vary according to the application. The techniques will be illustrated with several example applications or case studies from projects or applications I have been involves with. Issues such as interfacing between the FPGA and peripheral devices will be covered briefly, as will designing the system in such a way that it can be more readily debugged and tuned"-- |
| Assigning source |
Provided by publisher |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Embedded computer systems |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Field programmable gate arrays |