Fundamentals of digital logic with Verilog design / (Record no. 75159)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00918nam a2200253 a 4500 |
| 001 - CONTROL NUMBER | |
| control field | vtls000076991 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | KUKTEM |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20251125095830.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 140303t2014 nyua f 001 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9780073380544 |
| 039 #9 - LEVEL OF BIBLIOGRAPHIC CONTROL AND CODING DETAIL [OBSOLETE] | |
| Level of rules in bibliographic description | 201410171516 |
| Level of effort used to assign nonsubject heading access points | fawwaz |
| -- | 201403031135 |
| -- | dilla |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | UMP |
| 090 ## - LOCALLY ASSIGNED LC-TYPE CALL NUMBER (OCLC); LOCAL CALL NUMBER (RLIN) | |
| Classification number (OCLC) (R) ; Classification number, CALL (RLIN) (NR) | TK7868.L6 B76 2014 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Brown, Stephen D. |
| 245 10 - TITLE STATEMENT | |
| Title | Fundamentals of digital logic with Verilog design / |
| Statement of responsibility, etc. | Stephen Brown and Zvonko Vranesic |
| 250 ## - EDITION STATEMENT | |
| Edition statement | Third edition |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | Dubuque : |
| Name of publisher, distributor, etc. | McGraw-Hill Higher Education, |
| Date of publication, distribution, etc. | 2014 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | xvi, 847 p. : |
| Other physical details | ill. ; |
| Dimensions | 23 cm. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Logic circuits |
| General subdivision | Design and construction |
| -- | Data processing |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Verilog (Computer hardware description language) |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Computer |
| General subdivision | Aided design |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Vranesic, Zvonko G. |
| Withdrawn status | Lost status | Damaged status | Not for loan | Home library | Current library | Date acquired | Cost, normal purchase price | Total checkouts | Full call number | Barcode | Date last seen | Copy number | Cost, replacement price | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Not lost | UMPLIB PEKAN | UMPLIB PEKAN | 04/09/2019 | 711.58 | TK7868.L6 B76 2014 | 0000088030 | 04/09/2019 | 1 | 711.58 | 04/09/2019 | Open Shelf |