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Digital VLSI chip design with Cadence and Synopsys CAD tools / Erik Brunvand

By: Material type: TextTextPublication details: Boston, MA : Addison-Wesley, c2010Description: xvi, 571 p. : ill. ; 24 cmISBN:
  • 9781926567556
  • 0321547993
Subject(s):
Contents:
Introduction -- Cadence DFII and ICFB -- Composer schematic capture -- Verilog simulation -- Virtuoso layout editor -- Standard cell design template -- Spectre analog simulator -- Cell characterization -- Verilog synthesis -- Abstract generation -- SOC encounter place and route -- Chip assembly -- Design example -- Appendix A : Tool and setup scripts -- Appendix B : Scripts to drive the tools -- Appendix C : Technology and cell libraries
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Holdings
Item type Current library Call number Copy number Status Date due Barcode
Open Shelf Open Shelf UMPLIB PEKAN TK7874.75 .B78 2010 (Browse shelf(Opens below)) 1 Available 0000065265

Includes bibliographical references and index

Introduction -- Cadence DFII and ICFB -- Composer schematic capture -- Verilog simulation -- Virtuoso layout editor -- Standard cell design template -- Spectre analog simulator -- Cell characterization -- Verilog synthesis -- Abstract generation -- SOC encounter place and route -- Chip assembly -- Design example -- Appendix A : Tool and setup scripts -- Appendix B : Scripts to drive the tools -- Appendix C : Technology and cell libraries

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