02602nam a2200241 a 4500 vtls000040716 KUKTEM 20251114204453.0 090722t2008 my ao f m 000 0 eng d THE0006651(Local) 201905161514 amirul 201905161513 amirul 201107132155 VLOAD 200908141650 VLOAD 200907221754 kam UMP TJ1280 .T38 2008 rs Bc. Taufif Zakaria Dedicated fixture design for polishing of silicon / Taufif Bin Zakaria Dedicated fixture design for polishing of silicon [electronic resource] Kuantan, Pahang : UMP, 2008 45 p. : ill. (some col.) ; 30 cm. + 1 computer disc Project paper (Bachelor of Mechanical Engineering) -- Universiti Malaysia Pahang - 2008 Polishing of silicon is a major process seen in microelectronic and optical industries. As mirror-like surface finish is an essential factor that influences the performance of electronic and optical products, it has been believed that the fixture in finite element does play a role to produce such a quality surface on silicon. This paper centers on designing the fixture in finite element environment for polishing of silicon. Polishing process was virtually developed using general purpose FE codes. Process model consist of major components needed for polishing such as the base plate, the pad, the abrasive, silicon and of course of fixture. Currently only 2D model was considered because of the complexity of the process and limitation of the FE code. Fixed diamond abrasive proposed by VTT microelectronics was created in FE model to overcome the modeling difficulty of loose abrasives, to conveniently define polishing forces involved, and also investigated the effectiveness of the new abrasive design. Polishing forces were split into two-normal and tangential forces. The presence of micron-size diamond abrasive was modeled by defining friction coefficient at the interface between silicon and abrasive sheet. Typical values of polishing forces were defined as recommended by manufacturer. Finer mesh was designed at the top layer of the silicon in order to simulate the action of the diamond abrasive realistically. Polishing process was simulated by changing the various fixture designs. The goodness of the fixture design was justified by absence of high stress concentration in anywhere in the silicon. Grinding and polishing 0 0 0 1 20000 20000 2019-09-04 0 TJ1280 .T38 2008 rs Bc. 0000038190 2019-09-04 00:00:00 1 2019-09-04 PSM 0 0 0 1 20000 20000 2019-09-04 0 CD 3448 | TJ1280 .T38 2008 rs Bc. 0000038191 2019-09-04 00:00:00 1 2019-09-04 PSM VIRTUA40 2587 2593 VTLSSORT0080*0200*0400*0900*1000*2450*2460*2600*3000*5020*5200*6500*9992