00873nam a2200229 a 4500 vtls000019284 KUKTEM 20251117142426.0 070406 000 0 eng d 0387255389 201107131817 VLOAD 200908141204 VLOAD 200908141135 VLOAD 200908131617 VLOAD 200704060952 sri UMP TK7885.7 V37 2005 Verification methodology manual for System Verilog / Janick Bergeron New York : Springer , c2005 xvi, 503p. : ill, ; 24 cm. Includes bibliographical references and index Verilog (Computer hardware description language) Intergrated circuits Verification Bergeron, Janick. 0 0 lcc 0 0 20000 20000 2019-09-04 770.00 0 TK7885.7 V37 2005 0000022363 2019-09-04 00:00:00 1 770.00 2019-09-04 OPEN VIRTUA 28990 28996 VTLSSORT0080*0200*0900*2450*2600*3000*5040*6500*6501*7000*9991