01262nam a2200301 a 4500 vtls000030437 KUKTEM 20251117145144.0 080725t2007 nyua f bi 001 0 eng d 2006-939848 9780387300375 (cased) 0387300376 (cased) 201107132033 VLOAD 200908141503 VLOAD 200908141433 VLOAD 200908132018 VLOAD 200807250904 fauzi UMP TK7874.75 .S29 2007 Saxena, Prashant. Routing congestion in VLSI circuits : estimation and optimization / Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar. New York : Springer, c2007. xiv, 248 p. : ill. ; 24 cm. Series on integrated circuits and systems Includes bibliographical references and index. Integrated circuits Very large scale integration. Routing (Computer network management) Shelar, Rupesh S. Sapatnekar, Sachin S., 1967- Table of contents http://www.loc.gov/catdir/toc/fy0803/2006939848.html 0 0 0 0 20000 20000 2019-09-04 0 TK7874.75 .S29 2007 0000027943 2019-09-04 00:00:00 1 2019-09-04 OPEN VIRTUA40 40497 40503 VTLSSORT0080*0100*0200*0201*0400*0900*1000*2450*2600*3000*4400*5040*6500*6501*7000*7001*8560*9991