01391nam a2200313 a 4500 vtls000029349 KUKTEM 20251117145252.0 080610s2008 njua b 001 0 eng 0471704490 (cloth) 9780471704492 (cloth) 201107132058 VLOAD 200908141536 VLOAD 200908141506 VLOAD 200908132038 VLOAD 200806101136 norsaini UMP TK7874.58 .Y64 2008 Yoeli, Michael, 1917- Verification of systems and circuits using LOTOS, Petri Nets, and CCS / by Michael Yoeli and Rakefet Kol. Hoboken, N.J. : Wiley-Interscience, c2008. xv, 231 p. : ill. ; 25 cm. Wiley series on parallel and distributed computing Includes bibliographical references and index. Integrated circuits Verification. Computer software Verification. LOTOS (Computer program language) Petri nets. Kol, Rakefet. Table of contents only http://www.loc.gov/catdir/enhancements/fy0826/2007033487-t.html Contributor biographical information http://www.loc.gov/catdir/enhancements/fy0809/2007033487-b.html 0 0 0 0 20000 20000 2019-09-04 315.23 0 TK7874.58 .Y64 2008 0000033962 2019-09-04 00:00:00 1 315.23 2019-09-04 OPEN VIRTUA40 42767 42773 VTLSSORT0080*0200*0201*0400*0900*1000*2450*2600*3000*4400*5000*6500*6501*6502*6503*7000*8560*8561*9991