01318nam a2200313 a 4500 vtls000029294 KUKTEM 20251117145257.0 080604s2008 enka b 001 0 eng 9780470060704 0470060700 201107132104 VLOAD 200908141544 VLOAD 200908141515 VLOAD 200908132043 VLOAD 200806041546 norsaini UMP TK7885.7 .M54 2008 Minns, Peter D. FSM-based digital design using Verilog HDL / Peter Minns, Ian Elliott. Finite state machine based digital design using Verilog HDL Synapticad : tools for the thinking mind [electronic resource] Chichester, England ; Hoboken, NJ : J. Wiley & Sons, c2008. xiii, 391 p. : ill. ; 26 cm. + 1 CD-ROM. Includes bibliographical references and index. Verilog (Computer hardware description language) Digital electronics. Sequential machine theory. Elliott, Ian D. Table of contents only http://www.loc.gov/catdir/enhancements/fy0804/2007043838-t.html 0 0 0 0 20000 20000 2019-09-04 498.00 1 TK7885.7 .M54 2008 0000033981 2024-01-10 00:00:00 2023-12-22 1 498.00 2019-09-04 OPEN 0 0 0 0 20000 20000 2019-09-04 498.00 0 CD 2999 | TK7885.7 .M54 2008 0000033982 2019-09-04 00:00:00 1 498.00 2019-09-04 ACCOM VIRTUA40 42936 42942 VTLSSORT0080*0200*0201*0400*0900*1000*2450*2460*2461*2600*3000*5040*6500*6501*6502*7000*8560*9991 1