Brunvand, Erik creator text bibliography mau Boston, MA Addison-Wesley c2010 2010 monographic eng

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xvi, 571 p. : ill. ; 24 cm. Introduction -- Cadence DFII and ICFB -- Composer schematic capture -- Verilog simulation -- Virtuoso layout editor -- Standard cell design template -- Spectre analog simulator -- Cell characterization -- Verilog synthesis -- Abstract generation -- SOC encounter place and route -- Chip assembly -- Design example -- Appendix A : Tool and setup scripts -- Appendix B : Scripts to drive the tools -- Appendix C : Technology and cell libraries specialized Erik Brunvand Includes bibliographical references and index Integrated circuits Very large scale integration Computer-aided design 9781926567556 0321547993 UMP 111124 20251117145605.0 vtls000056278