Design of cost-efficient interconnect processing units :  spidergon STNoC / 
 Design of cost-efficient interconnect processing units  spidergon STNoC  [electronic resource] : 
Marcello Coppola ... [et al.] 
 - Boca Raton, FL :  Taylor & Francis ,  c2009 
 - xxi, 263 p. :  ill. ;  25 cm. +  1 computer disc 
 - System-on-chip design and technologies .
 - System-on-chip design and technologies .
<br/><br/>Includes bibliographical references and index 
<br/><br/><label>ISBN: </label>9781420044713 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Networks on a chip<br/>ST Microelectronics<br/>Microprocessors