Ker, Ming-Dou. creator Hsu, Sheng-Fu. text bibliography si Singapore Hoboken, NJ Piscataway, NJ] Wiley IEEE Press c2009 2009 monographic eng

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xiii, 249 p. : ill. ; 26 cm. "Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process." -- Publisher’s description Physical Mechanism of TLU under the System-Level ESD Test -- Component-Level Measurement for TLU under System-Level ESD Considerations -- TLU Dependency on Power-Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits -- TLU in CMOS ICs in the Electrical Fast Transient Test -- Methodology on Extracting Compact Layout Rules for Latchup Prevention -- Special Layout Issues for Latchup Prevention -- TLU Prevention in Power-Rail ESD Clamp Circuits -- Appendix A: Practical Application Extractions of Latchup Design Rules in a 0.18-mm 1.8 V/3.3V Silicided CMOS Process specialized Ming-Dou Ker and Sheng-Fu Hsu Includes bibliographical references and index Metal oxide semiconductors, Complementary Defects Metal oxide semiconductors, Complementary Reliability 9780470824078 0470824077 UMP 090904 20251117150433.0 vtls000043314