02042nam a2200253 a 4500 vtls000077299 KUKTEM 20251125102832.0 140407t2014 nyua f 001 0 eng d 9781461417606 (hbk.) 201507031655 aida 201506251156 aida 201404071448 irma UMP TK7867 .B35 2014 Balasinski, Artur Design for manufacturability: from 1D to 4D for 90-22 nm technology nodes / Artur Balasinski New York : Springer, 2014 viii, 278 p. : ill. (some col.) ; 24 cm. Includes bibliographical references Classic DfM: from 2D to 3D -- DfM at 28 nm and Beyond -- New DfM Domain: Stress Effects -- Conclusions and Future Work This book explains integrated circuit design for manufacturability (DfM) at the product level (packaging, applications) and applies engineering DfM principles to the latest standards of product development at 22 nm technology nodes. It is a valuable guide for layout designers, packaging engineers and quality engineers, covering DfM development from 1D to 4D, involving IC design flow setup, best practices, links to manufacturing and product definition, for process technologies down to 22 nm node, and product families including memories, logic, system-on-chip and system-in-package. Provides design for manufacturability guidelines on layout techniques for the most advanced, 22 nm technology nodes; Includes information valuable to layout designers, packaging engineers and quality engineers, working on memories, logic, system-on-chip and system-in-package; Offers a highly-accessible, single-source reference to information otherwise available only from disparate sources; Helps readers to translate reliability methodology into real design flows Electronic circuit design Integrated circuits Design 0 0 0 0 20000 20000 2019-09-04 394.96 0 TK7867 .B35 2014 0000098548 2019-09-04 00:00:00 1 394.96 2019-09-04 OPEN VIRTUA40 80025 80031 VTLSSORT0080*0200*0400*0900*1000*2450*2600*3000*5040*5050*5200*6500*6501*9992