TY  - BOOK
AU  - Taraate,Vaibbhav
TI  - Logic synthesis and SOC Prototyping: RTL design using VHDL 
SN  - 9789811513145
PY  - 2020///
CY  - Singapore
PB  - Springer
KW  - Systems on a chip
KW  - VHDL (Computer hardware description language)
N1  - Includes bibliographical references and index
UR  - https://link-springer-com.libraryumpsa.idm.oclc.org/search?query=+Logic+Synthesis+and+SOC+Prototyping
UR  - https://link.springer.com/book/10.1007/978-981-15-1314-5
ER  -