000 00885nam a2200229 a 4500
001 vtls000063628
003 KUKTEM
005 20251114204409.0
008 120906t2012 my a f m 000 0 eng d
020 _aTHE0006917(Local)
039 9 _a201906131049
_baida
_y201209061630
_zFida
040 _aUMP
090 _aTK7871.89.S35 S93 2012 r Thesis
100 0 _aAhmad Syahiman Mohd Shah
245 1 0 _aPattern layout optimization for low series resistance and capacitance in gan schottky barrier diodes /
_cAhmad Syahiman Mohd Shah
260 _aFukui, Japan :
_bUniversity of Fukui,
_c2012
300 _a70 p. :
_bill. (some col.) ;
_c30 cm.
502 _aThesis (Master of Engineering) -- University of Fukui - 2012
504 _aBibliography: p. 66-70
650 0 _aDiodes, Schottky-barrier
999 _aVIRTUA40
_c1335
_d1341
999 _aVTLSSORT0080*0200*0400*0900*1000*2450*2600*3000*5020*5040*6500*9992