000			01937nam a2200241 a 4500
001			vtls000037641
003			KUKTEM
005			20251114204418.0
008			090611t2008 my a f m 000 0 eng|d
020			_aTHE0006895(Local)
039		9	_a201906131011 _baida _c201107132243 _dVLOAD _c200908141628 _dVLOAD _c200908141601 _dVLOAD _y200906111234 _zida84
040			_aUMP
090			_aTK7868.D5 S93 2008 rs Bc.
100	0		_aMuhammad Syafiq Norashid
245	1		_a16 bits x 16 bits booth multiplier using VHDL / _cMuhammad Syafiq Norashid
246	3		_a16 bits x 16 bits booth multiplier using VHDL _h[electronic resource]
260			_aKuantan, Pahang : _bUMP, _c2008
300			_a63 p. : _bill. (some col.) , _c30 cm. + _e1 computer disc
502			_aProject paper (Bachelor of Electrical Engineering (Electronics)) -- Universiti Malaysia Pahang - 2008
520	3		_aNowadays, digital device is very important to all the people in this world. The high speed operation and less space and energy required had made the digital devices more preferred. This project is to design digital system which performed fixed point Booth Multiplier where the design system would be developed using hardware description language (HDL), in this case, VHDL (VHSIC Hardware Description Language), VHSIC stands for Very High Speed Integrated Circuit. The Software used would be Xilinx ISE 10.1 which is the software used to designed digital system for Xilinx manufactured FPGA board. The algorithm to design the system is Booth Multiplier Algorithm. The designed digital system will receive two 16 bits input and processes it to create a 32 bits output with the value of the multiplied inputs data value. Finally, it is proven that the system created can calculate and yield a fixed point multiplied output of the input value.
650		0	_aDigital electronics
999			_aVIRTUA40 _c1584 _d1590
999			_aVTLSSORT0080*0200*0400*0900*1000*2450*2460*2600*3000*5020*5200*6500*9992