000			02099nam a2200241 a 4500
001			vtls000037710
003			KUKTEM
005			20251114204418.0
008			090612t2008 my a f m 000 0 eng|d
020			_aTHE0006894(Local)
039		9	_a201906131010 _baida _c201107132243 _dVLOAD _c200908141628 _dVLOAD _c200908141602 _dVLOAD _y200906121529 _zida84
040			_aUMP
090			_aTK7868.D5 R67 2008 rs Bc.
100	0		_aRosmira Roslan
245	1	0	_aChess digital clock / _cRosmira Binti Roslan
246	3		_aChess digital clock _h[electronic resource]
260			_aKuantan, Pahang : _bUMP, _c2008
300			_a44 p. : _bill. ; _c30 cm.
502			_aProject paper (Bachelor in Electrical Engineering (Electronics)) -- Universiti Malaysia Pahang - 2008
520	3		_aThe purpose of my project is to design and implement of the Chess Digital Clock. The project employs ISE software (ISE Design Suite 10.1) and implementation on Field-Programmable Gate Arrays (FPGAs) Xilinx board. It is a new technique for testing the interconnects of an arbitrary design mapped into an FPGA. Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. The experimental result on various benchmarks using the ISE software is on its simulation. The software is designed using VHDL code. Digital circuit modeling with hardware description languages (HDLs) is the key to modern design of integrated circuits (ICs). The state-of-the-art technique of designing complex digital systems and integrated circuits is to apply an HDL-based CAD approach, in which a high-level, text-based, abstract description of the circuit is created, then synthesized to a hardware implementation in a selected technology, and finally verified for its functionality and timing.
650		0	_aDigital electronics
999			_aVIRTUA40 _c1595 _d1601
999			_aVTLSSORT0080*0200*0400*0900*1000*2450*2460*2600*3000*5020*5200*6500*9992