000 00870nam a2200217 a 4500
001 vtls000005185
003 KUKTEM
005 20251117142118.0
008 060614 t2005 njua f 001 0 eng d
020 _a0131433474
039 9 _a201207031011
_bFida
_c201107131705
_dVLOAD
_c200908141031
_dVLOAD
_c200908141004
_dVLOAD
_y200606141122
_zVLOAD
040 _aUMP
090 _aTK7874.58 .L36 2005
100 1 _aLam, William K.
245 1 0 _aHardware design verification :
_bsimulation and formal method-based approaches /
_cWilliam K. Lam
260 _aUpper Saddle River, NJ :
_bPrentice Hall,
_c2005
300 _axxv, 585 p. :
_bill. ;
_c25 cm.
504 _aIncludes bibliographical references (p. 539-559) and index
650 0 _aIntegrated circuits
_xVerification
999 _aVIRTUA40
_c22657
_d22663
999 _aVTLSSORT0080*0200*0400*0900*1000*2450*2600*3000*5040*6500*9992