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001			vtls000020059
003			KUKTEM
005			20251117144316.0
008			070611 2006 xxu 000 0 eng d
020			_a0750679492
039		9	_a201107131917 _bVLOAD _c200908141322 _dVLOAD _c200908141254 _dVLOAD _c200908131705 _dVLOAD _y200706111622 _ztraining
040			_aUMP
090			_aQA76.76.D47 D78 2006
100	1		_aDrusinsky, Doron
245	1	0	_aModeling and verification using UML statecharts : _ba working guide to reactive system design, runtime monitoring and execution-based model checking / _cDoron Drusinsky
246	3		_aModeling and verification using UML statecharts _h[electronic resource] : _ba working guide to reactive system design, runtime monitoring and execution-based model checking
260			_aAmsterdam : _bNewnes, _c2006
300			_axii, 294, 302, 306p. : _bill. ; _c23 cm. + _e1 computer disc
505			_aCD-ROM contains : Diagrams and code for the example in Chapter 4, Runtime code for monitoring, Automatic white box test generation
650		0	_aUML (Computer science)
650		0	_aFormal methods (Computer science)
650		0	_aComputer software _xDevelopment
999			_aVIRTUA40 _c33635 _d33641
999			_aVTLSSORT0080*0200*0400*0900*1000*2450*2460*2600*3000*5050*6500*6501*6502*9991