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_a201107131912 _bVLOAD _c200908141316 _dVLOAD _c200908141248 _dVLOAD _c200908131702 _dVLOAD _y200704121229 _zfarina |
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| 040 | _aUMP | ||
| 090 | _aTK7874.75 .Q26 2005 | ||
| 100 | 1 |
_aQin, Zhanhai, _d1976- |
|
| 245 | 1 | 0 |
_aSymbolic analysis and reduction of VLSI circuits / _cZhanhai Qin, Sheldon X.D. Tan, Chung-Kuan Cheng |
| 260 |
_aNew York, NY : _bSpringer, _cc2005 |
||
| 300 |
_axxii, 283 p. : _bill. ; _c25 cm. |
||
| 504 | _aIncludes bibliographical references (p. [273]-280) and index | ||
| 650 | 0 |
_aIntegrated circuits _xVery large scale integration |
|
| 650 | 0 | _aSymbolic circuit analysis | |
| 700 | 1 | _aCheng, Chung-Kuan | |
| 700 | 1 | _aTan, Sheldon X. D. | |
| 856 | 0 | _uhttp://www.loc.gov/catdir/enhancements/fy0663/2005284555-d.html | |
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_aVIRTUA _c33815 _d33821 |
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