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001 vtls000020097
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008 070612t2006 caua f 000 0 eng d
020 _a0123705975
039 9 _a201207031141
_bFida
_c201107131917
_dVLOAD
_c201105271101
_dFida
_c200908141323
_dVLOAD
_y200706121422
_ztraining
040 _aUMP
090 _aTK7874.75 .V57 2006
245 0 0 _aVLSI test principles and architectures :
_bdesign for testability /
_cedited by Laung-Tern Wang, Cheng-Wen Wu, Xiaoqing Wen
260 _aSan Fransisco, CA :
_bMorgan Kaufmann,
_c2006
300 _a777 p. :
_bill. ;
_c24 cm.
650 0 _aIntegrated circuits
_xVery large scale integration
_xTesting
650 0 _aIntegrated circuits
_xVery large scale integration
_xDesign
700 1 _aWang, Laung-Terng
700 1 _aWu, Cheng-Wen
700 1 _aWen, Xiaoqing
999 _aVIRTUA40
_c34158
_d34164
999 _aVTLSSORT0080*0200*0400*0900*2450*2600*3000*6500*6501*7000*7001*7002*9992