000 01112nam a22002657a 4500
001 vtls000020212
003 KUKTEM
005 20251117144338.0
008 070627 2006 flu 000 0 eng d
020 _a9780849379239
039 9 _a201107131918
_bVLOAD
_c200908141324
_dVLOAD
_c200908141256
_dVLOAD
_c200908131706
_dVLOAD
_y200706271407
_zkam
040 _aUMP
090 _aTK7874 .E33 2006
245 0 0 _aEDA for IC system design, verification, and testing /
_cedited by Louis Scheffer, Luciano Lavagno, Grant Martin
260 _aBoca Raton, FL :
_bCRC Taylor & Francis,
_c2006
300 _a1 v. (various pagings) :
_bill. ;
_c27 cm.
440 0 _aElectronic design automation for integrated circuits handbook
650 0 _aIntegrated circuits
_xComputer-aided design
650 0 _aIntegrated circuits
_xVerification
_xData processing
700 1 _aScheffer, Louis
700 1 _aLavagno, Luciano
700 1 _aMartin, Grant
856 4 2 _ahttp://www.loc.gov/catdir/enhancements/fy0654/2005052924-d.html
999 _aVIRTUA40
_c34434
_d34440
999 _aVTLSSORT0080*0200*0900*2450*2600*3000*4400*6500*6501*7000*7001*7002*8560*9991