000 00773nam a2200229 a 4500
001 vtls000024028
003 KUKTEM
005 20251117144502.0
008 080211t2007 nju f 001 0 eng|d
020 _a9780470052624
039 9 _a201107131952
_bVLOAD
_c200908141406
_dVLOAD
_c200908141338
_dVLOAD
_c200908131733
_dVLOAD
_y200802111229
_zkam
040 _aUMP
090 _aTK7885.7 .V345 2007
100 1 _aVahid, Frank
245 1 0 _aVerilog for digital design /
_cFrank Vahid, Roman Lysecky
260 _aHoboken, NJ :
_bWiley,
_c2007
300 _a173 p. :
_bill. ;
_c24 cm.
650 0 _aVHDL (Computer hardware description language)
700 1 _aLysecky, Roman
999 _aVIRTUA40
_c37256
_d37262
999 _aVTLSSORT0080*0200*0400*0900*1000*2450*2600*3000*6500*7000*9991
942 0 0 _01