000 01009nam a2200265 a 4500
001 vtls000036209
003 KUKTEM
005 20251117145354.0
008 090518t2009 maua f 001 0 eng d
020 _a9780123743640
039 9 _a201107132125
_bVLOAD
_c200910271449
_dkam
_c200908141612
_dVLOAD
_c200908141545
_dVLOAD
_y200905181046
_zsaini
040 _aUMP
090 _aTK7867 .E44 2009
245 0 0 _aElectronic design automation :
_bsynthesis, verification, and test /
_cedited by Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting (Tim) Cheng
260 _aBurlington, MA :
_bMorgan Kaufmann ,
_c2009
300 _a934 p. :
_bill. ;
_c25 cm.
490 1 _aSystems on silicon
650 0 _aElectronic circuit design
_xData processing
650 0 _aComputer
_xAided design
700 1 _aWang, Laung-Terng
700 1 _aChang, Yao-Wen
700 1 _aCheng, Kwang-Ting
830 0 _aSystems on silicon
999 _aVIRTUA40
_c44851
_d44857
999 _aVTLSSORT0080*0200*0400*0900*2450*2600*4900*3000*6500*6501*7000*7001*7002*8300*9991