000 00916nam a2200241 a 4500
001 vtls000039257
003 KUKTEM
005 20251117145441.0
008 090701t2008 nyu f 001 0 eng d
020 _a9780387765297
039 9 _a201107132145
_bVLOAD
_c201008021254
_dFida
_c200908141641
_dVLOAD
_c200908141616
_dVLOAD
_y200907011619
_znadia
040 _aUMP
090 _aTK7885.7 .S64 2008
100 1 _aSpear, Chris
245 1 0 _aSystemverilog for verification :
_ba guide to learning the testbench language features /
_cChris Spear
250 _a2nd ed.
260 _aNew York :
_bSpringer,
_c2008
300 _axxxvi, 429 p. ;
_c24 cm.
504 _aIncludes bibliographical references and index
650 0 _aVerilog (Computer hardware description language)
650 0 _aIntegrated circuits
_xVerification
999 _aVIRTUA40
_c46494
_d46500
999 _aVTLSSORT0080*0200*0400*0900*1000*2450*2500*2600*3000*5040*6500*6501*9991