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008 090108t2007 nyua f b 001 0 eng d
020 _a9780387717388 (hbk. : alk. paper)
020 _a0387717382 (hbk. : alk. paper)
020 _a9780387717401 (ebook)
020 _a0387717404 (ebook)
039 9 _a201107132244
_bVLOAD
_c200908141654
_dVLOAD
_c200908141637
_dVLOAD
_c200908132133
_dVLOAD
_y200901081132
_zsaini
040 _aUMP
090 _aTK7885.7 .M56 2007
100 1 _aMintz, Mike
245 1 0 _aHardware verification with SystemVerilog :
_ban object-oriented framework /
_cMike Mintz, Robert Ekendahl
260 _aNew York, NY :
_bSpringer,
_cc2007
300 _axxii, 314 p. :
_bill. ;
_c26 cm.
504 _aIncludes bibliographical references and index
650 0 _aVerilog (Computer hardware description language)
650 0 _aIntegrated circuits
_xVerification
650 0 _aObject-oriented programming (Computer science)
700 1 _aEkendahl, Robert
856 4 1 _3Table of contents only
_uhttp://www.loc.gov/catdir/enhancements/fy0826/2007923923-t.html
999 _aVIRTUA40
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999 _aVTLSSORT0080*0200*0201*0202*0203*0400*0900*1000*2450*2600*3000*5040*6500*6501*6502*7000*8560*9991