000			01285nam a2200241 a 4500
001			vtls000056278
003			KUKTEM
005			20251117145605.0
008			111124t2010 maua f b 001 0 eng d
020			_a9781926567556
020			_a0321547993
039		9	_a201206131506 _bjamie _y201111241034 _zfarina
040			_aUMP
090			_aTK7874.75 .B78 2010
100	1		_aBrunvand, Erik
245	1	0	_aDigital VLSI chip design with Cadence and Synopsys CAD tools / _cErik Brunvand
260			_aBoston, MA : _bAddison-Wesley, _cc2010
300			_axvi, 571 p. : _bill. ; _c24 cm.
504			_aIncludes bibliographical references and index
505	0		_aIntroduction -- Cadence DFII and ICFB -- Composer schematic capture -- Verilog simulation -- Virtuoso layout editor -- Standard cell design template -- Spectre analog simulator -- Cell characterization -- Verilog synthesis -- Abstract generation -- SOC encounter place and route -- Chip assembly -- Design example -- Appendix A : Tool and setup scripts -- Appendix B : Scripts to drive the tools -- Appendix C : Technology and cell libraries
650		0	_aIntegrated circuits _xVery large scale integration _xComputer-aided design
999			_aVIRTUA40 _c49406 _d49412
999			_aVTLSSORT0080*0200*0201*0400*0900*1000*2450*2600*3000*5040*5050*6500*9991