000 01785nam a2200349 a 4500
001 vtls000033324
003 KUKTEM
005 20251117150432.0
008 081202t2008 njua f 001 0 eng d
020 _a0131860062 (pbk. : alk. paper)
020 _a9780131860063
039 9 _a201107132101
_bVLOAD
_c200908241602
_dfauzi
_c200908141540
_dVLOAD
_c200908141511
_dVLOAD
_y200812021245
_znadia
040 _aUMP
090 _aTK7870.23 .L39 2008
100 1 _aLawday, Geoff
245 1 2 _aA signal integrity engineer's companion :
_breal-time test and measurement and design simulation /
_cGeoff Lawday, David Ireland, and Greg Edlund
260 _aUpper Saddle River, NJ :
_bPrentice Hall,
_cc2008
300 _axxxi, 460 p. :
_bill. ;
_c25 cm.
490 1 _aPrentice Hall modern semiconductor design series
500 _aIncludes index
505 0 _aChip-to-chip timing and simulation -- Signal path analysis as a signal integrity -- DDR2 case study -- Real-time measurements : probing -- Testing and debugging : oscilloscopes and logic analysers -- Replicating real-world signals with signal sources -- Signal analysis and compliance -- PCI express case study -- The wireless signal
650 0 _aElectronic apparatus and appliances
_xTesting
650 0 _aElectronic apparatus and appliances
_xDesign and construction
650 0 _aSignal processing
_xSimulation methods
650 0 _aSwitching circuits
_xReliability
650 0 _aOscillators, Electric
_xTesting
650 0 _aSignal integrity (Electronics)
700 1 _aIreland, David
700 1 _aEdlund, Greg
830 0 _aPrentice Hall modern semiconductor design series
999 _aVIRTUA40
_c58281
_d58287
999 _aVTLSSORT0080*0200*0201*0400*0900*1000*2450*2600*3000*4900*5000*5050*6500*6501*6502*6503*6504*6505*7000*7001*8300*9991