000 01199nam a2200253 a 4500
001 vtls000075465
003 KUKTEM
005 20251125095603.0
008 131017t2009 enka f 001 0 eng d
020 _a9780521859721 (hardback)
020 _a0521859727 (hardback)
039 9 _a201407071019
_bsaini
_y201310171108
_zida
040 _aUMP
090 _aTK7874.58 .P73 2009
245 0 0 _aPractical design verification /
_cedited by Dhiraj K. Pradhan, Ian G. Harris
260 _aCambridge :
_bCambridge University Press,
_c2009
300 _axi, 276 p. :
_bill. ;
_c26 cm.
504 _aIncludes bibliographical references and index
505 0 _aModel checking and equivalence checking -- Transaction-level system modeling -- Response checkers, monitors, and assertions -- System debugging strategies -- Test generation and coverage metrics -- SystemVerilog and Vera in a verification flow -- Decision diagrams for verification -- Boolean satisfiability and EDA applications
650 0 _aIntegrated circuits
_xVerification
700 1 _aPradhan, Dhiraj K.
700 1 _aHarris, Ian G.
999 _aVIRTUA40
_c72842
_d72848
999 _aVTLSSORT0080*0200*0201*0400*0900*2450*2600*3000*5040*5050*6500*7000*7001*9992