000 01025nam a2200265 a 4500
001 vtls000079409
003 KUKTEM
005 20251125100031.0
008 140603t2013 maua f 001 0 eng d
020 _a9780262019668
020 _a0262019663
039 9 _a201411201256
_bsaini
_y201406031153
_zfauzi
040 _aUMP
090 _aTK7885.7 .P43 2013
100 1 _aPedroni, Volnei A.
245 1 0 _aFinite state machines in hardware :
_btheory and design (with VHDL and SystemVerilog) /
_cVolnei A. Pedroni
260 _aCambridge, MA :
_bMIT Press,
_c2013
300 _ax, 337 p. :
_bill. ;
_c24 cm.
504 _aIncludes bibliographical references and index
650 0 _aSystemVerilog (Computer hardware description language)
650 0 _aVHDL (Computer hardware description language)
650 0 _aSequential machine theory œx Data processing
650 0 _aComputer systems œx Mathematical models
999 _aVIRTUA40
_c76915
_d76921
999 _aVTLSSORT0080*0200*0201*0400*0900*1000*2450*2600*3000*5040*6500*6501*6502*6503*9992