000			02042nam a2200253 a 4500
001			vtls000077299
003			KUKTEM
005			20251125102832.0
008			140407t2014 nyua f 001 0 eng d
020			_a9781461417606 (hbk.)
039		9	_a201507031655 _baida _c201506251156 _daida _y201404071448 _zirma
040			_aUMP
090			_aTK7867 .B35 2014
100	1		_aBalasinski, Artur
245	1	0	_aDesign for manufacturability: _bfrom 1D to 4D for 90-22 nm technology nodes / _cArtur Balasinski
260			_aNew York : _bSpringer, _c2014
300			_aviii, 278 p. : _bill. (some col.) ; _c24 cm.
504			_aIncludes bibliographical references
505	0		_aClassic DfM: from 2D to 3D -- DfM at 28 nm and Beyond -- New DfM Domain: Stress Effects -- Conclusions and Future Work
520			_aThis book explains integrated circuit design for manufacturability (DfM) at the product level (packaging, applications) and applies engineering DfM principles to the latest standards of product development at 22 nm technology nodes. It is a valuable guide for layout designers, packaging engineers and quality engineers, covering DfM development from 1D to 4D, involving IC design flow setup, best practices, links to manufacturing and product definition, for process technologies down to 22 nm node, and product families including memories, logic, system-on-chip and system-in-package. Provides design for manufacturability guidelines on layout techniques for the most advanced, 22 nm technology nodes; Includes information valuable to layout designers, packaging engineers and quality engineers, working on memories, logic, system-on-chip and system-in-package; Offers a highly-accessible, single-source reference to information otherwise available only from disparate sources; Helps readers to translate reliability methodology into real design flows
650		0	_aElectronic circuit design
650		0	_aIntegrated circuits _xDesign
999			_aVIRTUA40 _c80025 _d80031
999			_aVTLSSORT0080*0200*0400*0900*1000*2450*2600*3000*5040*5050*5200*6500*6501*9992