| 000 | 01041nam a2200313 a 4500 | ||
|---|---|---|---|
| 001 | vtls000104022 | ||
| 003 | KUKTEM | ||
| 005 | 20251125103915.0 | ||
| 008 | 180628t20182018fi a f 001 0 eng d | ||
| 020 |
_a9781138099951 _qhardcover |
||
| 039 | 9 |
_a201810171140 _bzul _y201806281558 _znadia |
|
| 040 |
_aUMP _beng _cUMP _erda |
||
| 090 | _aTK7868.D5 C39 2018 | ||
| 100 | 1 |
_aCavanagh, Joseph, _eauthor. |
|
| 245 | 1 | 0 |
_aVerilog HDL design examples / _cJoseph Cavanagh |
| 250 | _a1st edition | ||
| 264 | 1 |
_aBoca Raton : _bCRC Press, _c2018 |
|
| 264 | 4 | _c© 2018 | |
| 300 |
_axv, 655 pages : _billustrations ; _c26 cm. |
||
| 336 |
_atext _2rdacontent |
||
| 337 |
_aunmediated _2rdamedia |
||
| 338 |
_avolume _2rdacarrier |
||
| 500 | _aIncludes index | ||
| 650 | 0 |
_aDigital electronics _xComputer-aided design |
|
| 650 | 0 | _aLogic design | |
| 650 | 0 | _aVerilog (Computer hardware description language) | |
| 999 |
_aVIRTUA40 _c89573 _d89579 |
||
| 999 | _aVTLSSORT0080*0200*0400*0900*1000*2450*2500*2640*2641*3000*3360*3370*3380*5000*6500*6501*6502*9992 | ||
| 942 | 0 | 0 | _01 |