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| 003 | MY-KuUP | ||
| 005 | 20251125105649.0 | ||
| 006 | a||||fs|||| 001 0 | ||
| 007 | cr ||||||||||| | ||
| 008 | 200328t20202 sz fs 001 0 eng d | ||
| 020 |
_a9783030415365 _qebook |
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| 040 |
_aOhioLINK _beng _epn _erda _cUMP |
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| 090 | _aTK7874 .C36 2020 | ||
| 100 | 1 |
_aCanelas, António Manuel Lourenco, _eauthor. |
|
| 245 | 1 | 0 |
_aYield-aware analog IC design and optimization in nanometer-scale technologies / _cby António Manuel Lourenço Canelas, Jorge Manuel Correia Guilherme, Nuno Cavaco Gomes Horta |
| 264 | 1 |
_aCham : _bSpringer, _c2020 |
|
| 264 | 4 | _c© 2020 | |
| 300 | _a1 online resource | ||
| 336 |
_atext _2rdacontent |
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| 337 |
_acomputer _2rdamedia |
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| 338 |
_aonline resource _2rdacarrier |
||
| 650 | 0 |
_aIntegrated circuits _xDesign and construction |
|
| 700 | 1 |
_aGuilherme, Jorge Manuel Correia, _eauthor. |
|
| 700 | 1 |
_aHorta, Nuno Cavaco Gomes, _eauthor. |
|
| 856 | 4 | 0 |
_uhttps://link-springer-com.libraryumpsa.idm.oclc.org/book/10.1007/978-3-030-41536-5 _zOff-Campus link |
| 856 | 4 | 0 |
_uhttps://link.springer.com/book/10.1007/978-3-030-41536-5 _zClick here to access (Direct Link) |
| 942 |
_2lcc _cEBOOK |
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