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_c93604 _d93610 |
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| 003 | MY-KuUP | ||
| 005 | 20251125105654.0 | ||
| 006 | a||||fs|||| 001 0 | ||
| 007 | c| ||||||||||| | ||
| 008 | 201202t20202020si |||fs|||| 001 0 eng d | ||
| 020 |
_a9789811513145 _qebook |
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| 040 |
_aWorldCat _beng _cUMP _erda |
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| 090 | _aTK7895.E42 T37 2020 | ||
| 100 | 1 |
_aTaraate, Vaibbhav, _eauthor. |
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| 245 | 1 | 0 |
_aLogic synthesis and SOC Prototyping : _bRTL design using VHDL / _cVaibbhav Taraate |
| 264 | 1 |
_aSingapore : _bSpringer, _c2020 |
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| 264 | 4 | _c© 2020 | |
| 300 | _a1 online resource | ||
| 336 |
_atext _2rdacontent |
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| 337 |
_acomputer _2rdamedia |
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| 338 |
_aonline resource _2rdacarrier |
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| 504 | _aIncludes bibliographical references and index | ||
| 650 | 0 | _aSystems on a chip | |
| 650 | 0 | _aVHDL (Computer hardware description language) | |
| 856 | 4 | 0 |
_uhttps://link-springer-com.libraryumpsa.idm.oclc.org/search?query=+Logic+Synthesis+and+SOC+Prototyping _zOff-Campus link |
| 856 | 4 | 0 |
_uhttps://link.springer.com/book/10.1007/978-981-15-1314-5 _zClick here to access (Direct Link) |
| 942 |
_2lcc _cEBOOK |
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