| 000 | 01043nam a2200277 i 4500 | ||
|---|---|---|---|
| 999 |
_c93712 _d93718 |
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| 003 | MY-KuUP | ||
| 005 | 20251125105700.0 | ||
| 006 | a||||fs|||| 00| 0 | ||
| 007 | cr ||||||||||| | ||
| 008 | 200616s2020 si ob 000 0 eng d | ||
| 020 |
_a9789811544057 _qebook |
||
| 040 |
_aOhioLINK _beng _cUMP _erda |
||
| 090 | _aTK7885.7 .T37 2020 | ||
| 100 | 1 |
_aTaraate, Vaibbhav, _eauthor. |
|
| 245 | 1 | 0 |
_aSystemVerilog for hardware description : _bRTL design and verification / _cVaibbhav Taraate |
| 264 | 1 |
_aSingapore : _bSpringer, _c2020 |
|
| 300 | _a1 online resource | ||
| 336 |
_atext _2rdacontent |
||
| 337 |
_acomputer _2rdamedia |
||
| 338 |
_aonline resource _2rdacarrier |
||
| 504 | _aIncludes bibliographical references | ||
| 650 | 0 | _aSystemVerilog (Computer hardware description language) | |
| 856 | 4 | 0 |
_uhttps://link-springer-com.libraryumpsa.idm.oclc.org/book/10.1007/978-981-15-4405-7 _zOff-Campus link |
| 856 | 4 | 0 |
_uhttps://link.springer.com/book/10.1007/978-981-15-4405-7 _zClick here to access (Direct Link) |
| 942 |
_2lcc _cEBOOK |
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