Design for manufacturability: from 1D to 4D for 90-22 nm technology nodes / Artur Balasinski

By:

Balasinski, Artur

Material type: Text

TextPublication details: New York : Springer, 2014Description: viii, 278 p. : ill. (some col.) ; 24 cmISBN:

9781461417606 (hbk.)

Subject(s):

Contents:

Classic DfM: from 2D to 3D -- DfM at 28 nm and Beyond -- New DfM Domain: Stress Effects -- Conclusions and Future Work

Summary: This book explains integrated circuit design for manufacturability (DfM) at the product level (packaging, applications) and applies engineering DfM principles to the latest standards of product development at 22 nm technology nodes. It is a valuable guide for layout designers, packaging engineers and quality engineers, covering DfM development from 1D to 4D, involving IC design flow setup, best practices, links to manufacturing and product definition, for process technologies down to 22 nm node, and product families including memories, logic, system-on-chip and system-in-package. Provides design for manufacturability guidelines on layout techniques for the most advanced, 22 nm technology nodes; Includes information valuable to layout designers, packaging engineers and quality engineers, working on memories, logic, system-on-chip and system-in-package; Offers a highly-accessible, single-source reference to information otherwise available only from disparate sources; Helps readers to translate reliability methodology into real design flows

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Holdings ( 1 )
Title notes ( 3 )

Holdings
Item type	Current library	Call number	Copy number	Status	Date due	Barcode
Open Shelf	UMPLIB PEKAN	TK7867 .B35 2014 (Browse shelf(Opens below))	1	Available		0000098548

Includes bibliographical references

Classic DfM: from 2D to 3D -- DfM at 28 nm and Beyond -- New DfM Domain: Stress Effects -- Conclusions and Future Work

This book explains integrated circuit design for manufacturability (DfM) at the product level (packaging, applications) and applies engineering DfM principles to the latest standards of product development at 22 nm technology nodes. It is a valuable guide for layout designers, packaging engineers and quality engineers, covering DfM development from 1D to 4D, involving IC design flow setup, best practices, links to manufacturing and product definition, for process technologies down to 22 nm node, and product families including memories, logic, system-on-chip and system-in-package. Provides design for manufacturability guidelines on layout techniques for the most advanced, 22 nm technology nodes; Includes information valuable to layout designers, packaging engineers and quality engineers, working on memories, logic, system-on-chip and system-in-package; Offers a highly-accessible, single-source reference to information otherwise available only from disparate sources; Helps readers to translate reliability methodology into real design flows