Optimal channel dimensions and temperature characteristics of SI-FinFET transistor / Yousif Atalla Yousif

Faculty of Engineering Technology

Thesis (Master of Science) -- Universiti Malaysia Pahang – 2019

Includes bibliographical references

As metal oxide semiconductor field effect transistor (MOSFET) technology approaches its downscaling limits, many novel structures of FET have been explored extensively. One of the relatively new types of FET is FinFET. The performance of electronic devices, which may correspond to a wide array of recent applications, likely depend on the nano-dimensional characteristics of such devices. The chip generation of these powerful electronic devices with ultra-small transistors may increase in reliability when new findings from future research are consolidated. However, nano-dimensional FET designs and structures are still considered as novel technologies, thereby necessitating further study and improvement. Further innovations are needed despite the limitations in MOSFET science. Transistor-based temperature sensors are designed based on the temperature characteristics of current-voltage curves of FinFET transistors. This study aims to design channel dimensions of Si-FinFET for best performance based on electrical and temperature characteristics. The study investigates the temperature characteristics (sensitivity and stability) of Si-FinFET based on optimal channel dimensions, such as length (L), width (W)), oxide thickness (TOX) and operating voltage (VDD). This study focuses on simulating and analysing the effects of the operating temperature of Si-FinFET on its electrical characteristics as limitation factors, namely, threshold voltage (VT), subthreshold swing (SS), and drain-induced barrier lowering (DIBL). A multi-gate field effect transistor (MuGFET) simulation tool is used to investigate the temperature and electrical characteristics of FinFET. Current-voltage characteristics with different temperatures (T = 250, 275, 300, 325, 350, 375 and 400 K) and gate length (Lg = 25, 45, 65, 85 and 105 nm), gate width (Wg = 5, 10, 20, 40 and 80 nm) and oxide thickness (TOX = 1, 2, 3, 4 and 5 nm) are initially simulated. Then, the metal oxide semiconductor diode mode connection to measure FinFET temperature sensitivity is considered. Thus, the perfect channel length for the FinFET under the conditions considered in this thesis is 65 nm to obtain acceptable temperature sensitivity at the operating voltage range of 0–5 V. Furthermore, temperature sensitivity of the FinFET increased with channel width at the range of 5–80 nm. The best increments for the current (ΔI) in relation to temperature can be achieved by increasing TOX to 5 nm, beyond which the values become stable regardless of the thickness. We can infer that the optimal Wg values are 5, 10 and 20 nm, which are consistent and may be considered as perfect values. The best TOX in this study is 1 nm.